Vertical transistor memory cell and array
US8213226B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 7, 2009 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Mar 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/711
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion, wherein the source and drain regions are opposing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.