Methods of forming transistor gate constructions, methods of forming NAND transistor gate constructions, and methods forming DRAM transistor gate constructions
US8216935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2009 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Nov 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/664
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a transistor gate construction includes forming a gate stack comprising a sacrificial material received over conductive gate material. The gate stack has lateral sidewalls having insulative material received there-against. The sacrificial material is removed from being received over the conductive gate material to form a void space between the insulative material over the conductive gate material. Elemental tungsten is selectively deposited within the void space over the conductive gate material and a transistor gate construction forming there-from is formed there-from, and which has a conductive gate electrode which includes the conductive gate material and the elemental tungsten. The transistor gate might be used in NAND, DRAM, or other integrated circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.