Wafer planarity control between pattern levels
US8216945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2010 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Apr 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.