Parallel array architecture for constant current electro-migration stress testing

US8217671B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kanak B. Agarwal · Austin, US
• Peter A. Habitz · South Burlington, US
• Jerry D. Hayes · Georgetown, US
• Ying Liu · Austin, US
• Deborah M. Massey · Jericho, US
• Alvin W. Strong · South Burlington, US

Key dates

• Filing date: Jun 26, 2009
• Grant date: Jul 10, 2012
• Expiry date: Sep 23, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2858
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.