Mitigating context switch cache miss penalty
US8219780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2005 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Sep 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.