Patent · US Active

Memory read stability using selective precharge

US8223567B2 · kind B2 · utility

11Cited by

5References

14Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Mohamed H. Abu Rahma · San Diego, US
Ritu Chaba · San Diego, US
Nan Chen · San Diego, US
Sei Seung Yoon · San Diego, US

Key dates

Filing date	Dec 15, 2008
Grant date	Jul 17, 2012
Priority date	—
Expiry date	Feb 22, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.