Efficient word lines, bit line and precharge tracking in self-timed memory device
US8223572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2011 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Sep 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.