Semiconductor memory device
US8225150B2 · kind B2 · utility
2Cited by
12References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2011 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | May 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.