Methods and apparatuses for external voltage test methodology of input-output circuits
US8225156B1 · kind B1 · utility
3Cited by
107References
20Claims
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Key dates
| Filing date | Nov 24, 2010 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Nov 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318508
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.