Margin testing of static random access memory cells
US8228749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2010 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Apr 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.