Fully associative banking for memory
US8230154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2007 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Jan 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.