Test structure for determination of TSV depth
US8232115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Apr 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76898
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.