Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same
US8232654B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2011 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Jun 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.