SRAM delay circuit that tracks bitcell characteristics
US8233337B2 · kind B2 · utility
13Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Aug 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.