Patent · US Active

System-on-chip with master/slave debug interface

US8234531B2 · kind B2 · utility

4Cited by

13References

14Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventor

Albrecht Mayer · Deisenhofen, DE

Key dates

Filing date	Oct 27, 2010
Grant date	Jul 31, 2012
Priority date	—
Expiry date	Oct 27, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.