Constraint programming based method for bus-aware macro-block pin placement in a hierarchical integrated circuit layout
US8234615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2010 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Jan 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The CP formulation includes modeling detailed and discrete constraints required to achieve an optimal pin-assignment. A stochastic CSP solver is used to define the cost function on search points giving full assignments to all the variables. The macro-block pins are ultimately moved to computed locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.