Trace reconstruction for silicon validation of asynchronous systems-on-chip
US8234618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Nov 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.