Planar silicide semiconductor structure
US8236637B2 · kind B2 · utility
6Cited by
12References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2010 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Nov 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0174
Abstract
A planar silicide structure and method of fabrication is disclosed. A FET having a silicided raised source-drain structure is formed where the height of the source-drain structures are the same as the height of the gates, simplifying the process of forming contacts on the FET. One embodiment utilizes a replacement metal gate FET and another embodiment utilizes a gate-first FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.