Cung D. Tran
32Patents
7h-index
47Co-inventors
65Inventor score
Filing activity: Jan 7, 2008 → Sep 17, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8415250B2 | Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device | Electricity | 34 | Active |
| US9305835B2 | Formation of air-gap spacer in transistor | Electricity | 25 | Active |
| US8643122B2 | Silicide contacts having different shapes on regions of a semiconductor device | Electricity | 19 | Active |
| US9312185B2 | Formation of metal resistor and e-fuse | Electricity | 11 | Active |
| US9111962B1 | Selective dielectric spacer deposition for exposing sidewalls of a finFET | Electricity | 10 | Active |
| US8603881B1 | Raised trench metal semiconductor alloy formation | Electricity | 10 | Active |
| US9691658B1 | Contact fill in an integrated circuit | Electricity | 9 | Active |
| US9349836B2 | Fin end spacer for preventing merger of raised active regions | Electricity | 6 | Active |
| US8236637B2 | Planar silicide semiconductor structure | Electricity | 6 | Active |
| US8796099B2 | Inducing channel strain via encapsulated silicide formation | Electricity | 5 | Active |
| US9530684B2 | Method and structure to suppress finFET heating | Electricity | 2 | Active |
| US9331166B2 | Selective dielectric spacer deposition for exposing sidewalls of a finFET | Electricity | 2 | Active |
| US8603915B2 | Multi-stage silicidation process | Electricity | 1 | Active |
| US8492275B2 | Method to form uniform silicide by selective implantation | Electricity | 0 | Active |
| US8298934B2 | Structure and method of creating entirely self-aligned metallic contacts | Electricity | 0 | Active |
| US8652963B2 | MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture | Electricity | 0 | Active |
| US9368493B2 | Method and structure to suppress FinFET heating | Electricity | 0 | Active |
| US10833022B2 | Structure and method to improve overlay performance in semiconductor devices | Electricity | 0 | Active |
| US9397181B2 | Diffusion-controlled oxygen depletion of semiconductor contact interface | Electricity | 0 | Active |
| US9514992B2 | Unidirectional spacer in trench silicide | Electricity | 0 | Active |
| US9472415B2 | Directional chemical oxide etch technique | Electricity | 0 | Active |
| US9391175B2 | Fin end spacer for preventing merger of raised active regions | Electricity | 0 | Active |
| US7964923B2 | Structure and method of creating entirely self-aligned metallic contacts | Electricity | 0 | Active |
| US9059308B2 | Method of manufacturing dummy gates of a different material as insulation between adjacent devices | Electricity | 0 | Active |
| US8946081B2 | Method for cleaning semiconductor substrate | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.