Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor

US8236708B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Sasha Kweskin · Chesterfield, US
• Paul Edward Gee · San Jose, US
• Shankar Venkataraman · Santa Clara, US
• Kedar Sapre · Mountain View, US

Key dates

• Filing date: Aug 13, 2010
• Grant date: Aug 7, 2012
• Expiry date: Apr 9, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02271
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.