Dummy gate structure for gate last process
US8237227B2 · kind B2 · utility
7Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jun 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.