Stack package
US8237291B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Sep 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, a lower stack group, an upper stack group, and connection members. The lower stack group is attached to the upper surface of the substrate and includes at least two semiconductor chips which are stacked in a face-up type to form on or more steps. The upper stack group is disposed over the lower stack group and includes at least two semiconductor chips which are stacked in a face-down type in such a way as to form one or more steps whose direction mirrors the direction of the at least one step of the lower stack group. The connection members electrically connect the semiconductor chips of the lower and upper stack groups to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.