Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop
US8237475B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2008 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | May 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.