Methods and apparatus for reducing defect bits in phase change memory
US8238149B2 · kind B2 · utility
12Cited by
238References
20Claims
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Key dates
| Filing date | Mar 2, 2010 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Nov 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.