Hierarchical memory architecture to connect mass storage devices
US8239629B2 · kind B2 · utility
7Cited by
5References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Nov 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.