Command queuing for next operations of memory devices
US8239875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Apr 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and/or methods that facilitate transferring data between a processor component and memory components are presented. A transfer controller component facilitates controlling data transfers in part by receiving respective subsets of data from respective memory components and arranging the respective subsets of data based in part on a desired predefined data order. The processor component generates a transfer map that includes information to facilitate arranging data in a predefined order. The processor component generates respective subsets of commands that are provided to queue components in respective memory components to retrieve desired data from the respective memory components. Each memory component services the commands in its queue component in an independent and parallel manner, and transfers the data retrieved from memory to the transfer controller component, which can arrange the received data in a predefined order for transfer to the processor component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.