On-die anti-resonance structure for integrated circuit
US8243479B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2011 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Sep 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.