Non-volatile memory and method with write cache partition management methods
US8244960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Oct 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.