Boosted gate voltage programming for spin-torque MRAM array
US8248841B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2010 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Aug 5, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.