Memory controller having tables mapping memory addresses to memory modules
US8250330B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2004 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Jan 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.