Patent · US Active

Partitioned replacement for cache memory

US8250332B2 · kind B2 · utility

9Cited by

7References

27Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Erich James Plondke · Austin, US
Lucian Codrescu · Austin, US
Ajay Anant Ingle · Austin, US

Key dates

Filing date	Jun 11, 2009
Grant date	Aug 21, 2012
Priority date	—
Expiry date	Feb 10, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/1027
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.