Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
US8250505B1 · kind B1 · utility
4Cited by
23References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 4, 2009 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Aug 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.