Method for fabricating CMOS transistor

US8252650B1 · kind B1 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Feng-Yi Chang · Tainan, TW
• Yi-Po Lin · Tainan, TW
• Jiunn-Hsiung Liao · Tainan, TW
• Shang-Yuan Tsai
• Chih-Wen Feng · Tainan, TW
• Shui-Yen Lu · Tainan, TW
• Ching-Pin Hsu · Tainan, TW

Key dates

• Filing date: Apr 22, 2011
• Grant date: Aug 28, 2012
• Expiry date: Apr 22, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.