Optimized semiconductor packaging in a three-dimensional stack

US8253234B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Harry Barowski · Balingen, DE
• Thomas J. Brunschwiler · Thalwil, CH
• Hubert Harrer · Böblingen, DE
• Andreas Huber · Holzgerlingen, DE
• Bruno Michel · Thalwil, CH
• Tim Niggemeier · Laatzen, DE
• Stephan Paredes · Thalwil, CH
• Jochen Supper · Herrenberg, DE

Key dates

• Filing date: Oct 28, 2010
• Grant date: Aug 28, 2012
• Expiry date: Nov 3, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/09701
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.