Implied storage operation decode using redundant target address detection
US8255674B2 · kind B2 · utility
3Cited by
4References
20Claims
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Assignee
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Key dates
| Filing date | Jan 28, 2009 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | May 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic arrangement and method to support implied storage operation decode uses redundant target address detection, whereby target addresses of previous instructions are compared with the target address of the current instruction, and if equal, and the target addresses of previous instructions are not used as sources, the current instruction is decoded as a store instruction. This allows a redundant operation in an instruction set architecture to be redefined as a store instruction, freeing up opcodes normally used for store instructions to be used for other instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.