Interconnects for stacked non-volatile memory device and method
US8258020B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 2010 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Dec 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/84
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a vertical interconnect for a memory device. The method includes providing a substrate having a surface region and defining a cell region, a first peripheral region, and a second peripheral region. A first thickness of dielectric material is formed overlying the surface region. A first bottom wiring structure spatially configured to extend in a first direction is formed overlying the first dielectric material for a first array of devices. A second thickness of a dielectric material is formed overlying the first wiring structure. The method includes forming an opening region in the first peripheral region. The opening region is configured to extend in a portion of at least the first thickness of dielectric material and the second thickness of dielectric material to expose a portion of the first wiring structure and to expose a portion of the substrate. A second bottom wiring material is formed overlying the second thickness of dielectric material and filling the opening region to form a vertical interconnect structure in the first peripheral region. A second bottom wiring structure is formed from the second wiring material for a second array of devices. The secon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.