Patent · US Active

System and method for integrated circuit arrangement having a plurality of conductive structure levels

US8258628B2 · kind B2 · utility

1Cited by

3References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Martina Hommel · Munich, DE
Heinrich Koerner · Bruckmühl, DE
Markus Schwerd · Holzkirchen, DE
Martin Seck · Birkenfeld, DE

Key dates

Filing date	Sep 20, 2006
Grant date	Sep 4, 2012
Priority date	—
Expiry date	Dec 20, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.