Low voltage and low power memory cell based on nano current voltage divider controlled low voltage sense MOSFET
US8259518B2 · kind B2 · utility
19Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2010 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Dec 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.