Bumped chip package fabrication method and structure
US8263486B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2011 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Jun 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a bumped chip package includes forming a first seed layer on a dielectric layer, the dielectric layer comprising a dielectric layer opening exposing a substrate terminal of a substrate, the first seed layer being formed within the dielectric layer opening and on the substrate terminal. A circuit pattern is plated on the first seed layer, wherein an exposed portion of the first seed layer is exposed from the circuit pattern. The exposed portion of the first seed layer is removed by laser-ablation. By using a laser-ablation process, a chemical etching process is avoided thus eliminating the need to treat or dispose of chemical etching hazardous waste. Further, circuit pattern width erosion and undercut of the circuit pattern associated with a chemical etching process are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.