Planarized passivation layer for semiconductor devices
US8264088B2 · kind B2 · utility
2Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2011 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Jul 11, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.