Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8264091B2 · kind B2 · utility
94Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2009 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Nov 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; attaching a buffer interconnect to and over the substrate; forming an encapsulation over the substrate covering the buffer interconnect and the integrated circuit; and forming a via in the encapsulation and to the buffer interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.