Controlling AC disturbance while programming
US8264898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Jun 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.