System and method for detecting mask data handling errors
US8266553B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2008 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Jul 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/84
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in which verification elements are disposed. The verification elements include cells that are duplicates of at least some of the different types of cells in device region and can include structures that are duplicates of at least some of the types of structures in the device region. The patterns in verification region are used in the final verification process to identify mask data handling errors in a mask job deck. Because the patterns in verification region are easy to locate and identify, the time required to perform the final verification process is reduced and the chance of error in the final verification process is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.