Patent · US Active

SOI wafers having MxOy oxide layers on a substrate wafer and an amorphous interlayer adjacent the substrate wafer

US8268076B2 · kind B2 · utility

4Cited by

10References

7Claims

0Family size

Assignee

Siltronic AG · DE

Inventors

Thomas Schroeder · Berlin, DE
Peter Storck · Mehring, DE
Hans Joachim Muessig · Dresden, DE

Key dates

Filing date	May 13, 2010
Grant date	Sep 18, 2012
Priority date	—
Expiry date	Dec 14, 2030

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10T428/26
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.