Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
US8269283B2 · kind B2 · utility
15Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2009 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Sep 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/791
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.