Semiconductor package substrate structure and manufacturing method thereof
US8269354B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2010 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Nov 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.