Nonvolatile memory device and method of operating the same
US8270221B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2010 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Mar 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a cell string, including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, and memory cells coupled in series between the drain select transistor and the source select transistor, a latch unit, including a first latch for storing a detection result of a threshold voltage of a second memory cell adjacent to a first memory cell selected from among the memory cells and a second latch for storing a detection result of a threshold voltage of the first memory cell, and a first reset unit electrically coupled between the first and second latches and configured to reset the second latch, during a time in which a read operation is performed on the first memory cell, in response to a first reset signal and the detection result stored in the first latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.