Memory device with improved switching speed and data retention
US8274073B2 · kind B2 · utility
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1References
22Claims
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Key dates
| Filing date | Mar 11, 2005 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Oct 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/311
Abstract
The present memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the passive layer and the second electrode. In undertaking an operation on the memory device, ions moves into within and from within the active layer, and the active layer is oriented so that the atoms of the active layer provide minimum obstruction to the movement of the ions into, within and from the active layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.