Read disturb free SMT MRAM reference cell circuit
US8274819B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 4, 2010 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Dec 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.