Semiconductor structures and methods of manufacturing the same
US8278164B2 · kind B2 · utility
17Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2010 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Oct 31, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.